Sudeep Bhoja

In an August 2025 post, Bhoja argued that the growing cost of AI inference stems from memory, not just compute, and described d-Matrix's early decision to focus on transformer inference with a chiplet-based Corsair accelerator. The post announced 3DIMC on the roadmap and said the first 3DIMC silicon, Pavehawk, was operating in the lab.2

At Hot Chips 2026, Bhoja previewed the 3D DRAM approach used in Raptor, which joins a DRAM memory chip and an SRAM compute chip into a single stacked unit.3

d-Matrix builds memory-centric hardware for AI inference. Its Corsair accelerator uses a chiplet-based digital in-memory compute design, and in August 2025 the company added 3D stacked digital in-memory compute (3DIMC) to its roadmap with Pavehawk, its first 3DIMC silicon.2

In September 2026 d-Matrix announced a collaboration with NVIDIA built around an NVLink Fusion rack-level system and introduced Raptor, a follow-on platform that stacks DRAM on an SRAM compute chip. In October 2026 it announced Squadron, a fleet of multi-rack inference systems, and said its Corsair servers and SquadRacks were generally available.34