Krste Asanović
Co-founder and Chief Architect of SiFive; RISC-V co-creator and UC Berkeley Professor Emeritus
- Co-founder and Chief Architect, SiFive312
- Chief Architect; co-founded its predecessor, the RISC-V Foundation, in 2015, RISC-V International12
- Professor Emeritus and Professor of the Graduate School, EECS; Co-Director of the SLICE Lab, University of California, Berkeley12
Krste Asanović is a co-founder and the Chief Architect of SiFive, the Chief Architect at RISC-V International, and a Professor Emeritus and Professor of the Graduate School in UC Berkeley's EECS Department. Asanović has led the RISC-V open instruction set architecture project at Berkeley since its start in 2010, and co-founded both SiFive and the RISC-V Foundation in 2015 to commercialize and standardize RISC-V.123
Academic career
Asanović received a PhD in computer science from UC Berkeley in 1998 and then joined the faculty at MIT, receiving tenure in 2005. Asanović returned to the Berkeley faculty in 2007, co-founding the Berkeley Parallel Computing Laboratory (Par Lab), leading the ASPIRE Lab, and co-leading the ADEPT and SLICE labs.21
Asanović's research covers computer architecture, VLSI design, parallel programming and operating system design. Projects listed on Asanović's page include the Chisel hardware construction language, the FireSim and FireBox datacenter-scale projects, and the Gemmini generator for systolic-array neural-network accelerators.1
RISC-V and SiFive
RISC-V began as a Berkeley summer project in 2010, created by Asanović, Andrew Waterman and Yunsup Lee with David Patterson as a free and open instruction set. The project started in Par Lab, continued in ASPIRE and then ADEPT, and its standard is now managed by RISC-V International, where Asanović is Chief Architect.412
In 2015 Asanović co-founded SiFive to commercialize RISC-V processors and co-founded the RISC-V Foundation, which became RISC-V International. SiFive's leadership page lists Asanović as Co-Founder and Chief Architect.243
Work
RISC-V instruction set architecture (external site: www2.eecs.berkeley.edu)Published research
Led the RISC-V project at Berkeley from 2010 and co-authored, with Andrew Waterman, Yunsup Lee and David Patterson, the 2011 technical report specifying the base user-level ISA.254
Rocket Chip Generator (external site: github.com)Open-source code
First-listed author of the 2016 Berkeley technical report describing the Rocket Chip generator for RISC-V systems-on-chip, whose open-source repository is maintained under CHIPS Alliance.67
Chipyard (external site: people.eecs.berkeley.edu)Open-source code
Asanović's page lists Chipyard as an active research project since 2019: a framework for designing and evaluating full systems-on-chip that integrates the Rocket and BOOM RISC-V core generators, the Gemmini neural-network accelerator generator and the FireSim FPGA-accelerated simulator.1
Career timeline
1998
Received a PhD in computer science from UC Berkeley, before joining the MIT faculty.2
2005
Received tenure at MIT.2
2007
Returned to the UC Berkeley faculty and co-founded the Par Lab.2
2010
Began leading the RISC-V open instruction set architecture project at Berkeley.21
May 13, 2011
Co-authored the first RISC-V Instruction Set Manual technical report on the base user-level ISA.5
2015
Apr 15, 2016
Published the Rocket Chip Generator technical report with Berkeley colleagues.6
2019
Chipyard and Gemmini began as active research projects listed on Asanović's page.1
Other documented roles
Roles the sources document but that are not confirmed as current.
- Faculty member, receiving tenure in 2005, before returning to Berkeley in 2007, Massachusetts Institute of Technology2
Honors and recognition
Related people
More sourced profiles at the same organization, in the same field, or from the same school.
- Alexei A. EfrosAlso at University of California, Berkeley
- Aaron TeoChips and hardware
- Adam GleaveAlso from UC Berkeley
- Ali GhodsiAlso at University of California, Berkeley
- Andrew BosworthChips and hardware
- Alex RivesAlso at MIT
- Anca DraganAlso at University of California, Berkeley
- Andrew FeldmanChips and hardware
- Alex SmolaAlso from UC Berkeley
- Andrew WatermanAlso at SiFive
- Andy BechtolsheimChips and hardware
- Alexander AminiAlso at Massachusetts Institute of Technology
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